1. Field of the Invention
This invention relates to integrated circuit structures, and in particular, it relates to dielectric materials used within dynamic random access memory cells formed on semiconductor integrated circuits.
2. Background Art
In a conventional transistor a gate is separated from the source and drain by a dielectric layer. When a sufficient voltage level is applied to the gate the transistor turns on and current flows between the source and the drain of the transistor. In a similar manner, when conductors of integrated circuits pass over dielectric layers located above adjacent n-wells or diffusion regions they can cause leakage current to flow between the n-wells or between the diffusion regions. This leakage current is very undesirable.
It is well known in the art of semiconductor fabrication that dielectric layers formed from organic sources can have shifts in their threshold voltage due to impurities in the dielectric material. The impurities are present in the layer because of the organic processes, such as ozone-TEOS based chemistry, which are used to form the material of the dielectric layer.
It is also known for the impurities in the dielectric layer to diffuse and collect at interfaces close to the substrate during high temperature processing steps performed after deposition of dielectric material formed with organometallic precursors. This diffusion can seriously degrade integrated circuit operation.
It is therefore an object of the present invention to provide a process for forming dielectric material for semiconductor fabrication using organic chemistry such as ozone-TEOS based chemistry and organometallic precursors which leave undesirable impurities in the dielectric material.
It is a further object of the present invention to eliminate or reduce threshold voltage shift caused by impurities that are a consequence of the organic processes for forming the dielectric layer.
It is a further object of the present invention to provide such a process for BPSG films that are thicker than at least 5 KA.
It is a further object of the present invention to prevent the problems associated with diffusion of impurities in dielectric layers to interfaces near the surface of the substrate.
These and other objects and advantages of the invention will become more fully apparent from the description and claims which follow or may be learned by the practice of the invention.
A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A barrier layer and a dielectric layer are deposited over the nonconducting region and over the active regions. Heat is applied to the integrated circuit causing the barrier layer to anneal. The dielectric layer can be a BPSG film. Preferably BPSG films are deposited using organometallic precursors. More specifically, ozone (4 to 20% vol conc.), TEOS, TEPO (as an example of a P source) and TEB (as an example of a B source) are reacted at a temperature of at least 300xc2x0 C. such that BPSG films of at least one thousand angstroms are formed at a deposition rate in the range of 500 angstroms/min to 6000 angstroms/min using gas or liquid injection for carrying the species into the reaction chamber. The preferred deposition temperature range is 300xc2x0 C.-600xc2x0 C. The deposition may be done at atmospheric or subatmospheric pressure, in a plasma or a non-plasma based reactor and deposition conditions and the dopant concentration can be varied to obtain the desired film properties and composition. Hot wall reactors can also be used for BPSG film deposition.